library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity twoWireTestbench is
end twoWireTestbench;

architecture test of twoWireTestbench is

  component twoWireInterface is
    Port( I2C_Clk : inout std_logic;
          I2C_Data : inout std_logic;
          FPGA_Clk : in std_logic;
          Sync : in std_logic);
  end component;

  signal clk : std_logic:='1';
  signal i2c_clk,i2c_data,sync : std_logic;

begin
  
  clk<= not clk after 20 ns;
  sync<= '1';
  
  UUT: twoWireInterface port map (i2c_clk,i2c_data,clk,sync);
  
end test;
